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lap-b controller link access procedure balanced mode the m pd72107 is an lsi that supports lap-b protocol specified by the itu-t recommended x.25 on a single chip. mos integrated circuit m pd72107 document no. s12962ej5v0ds00 (5th edition) date published october 1998 n cp(k) printed in japan the information in this document is subject to change without notice. 1998 data sheet features ? complied with itu-t recommended x.25 (lap-b84 edition) hdlc frame control sequence control flow control ? itu-t recommended x.75 supported ? ttc standard jt-t90 supported ? optional functions option frame global address frame error check deletion frame ? powerful test functions data loopback function loopback test link function frame trace function ? abundant statistical information ? detailed mode setting function ? modem control function ? on-chip dmac (direct memory access controller) 24-bit address byte/word transfer enabled (switch with external pin) ? memory-based interface memory-based command memory-based status memory-based transmit/receive data ? max.4 mbps serial transfer rate ? nrz, nrzi coding ordering information part number package m pd72107cw 64-pin plastic shrink dip (750 mils) m pd72107gc-3b9 80-pin plastic qfp (14 x 14 mm) m pd72107l 68-pin plastic qfj (950 x 950 mils)
2 m pd72107 block diagram name function bus interface an interface between the m pd72107 and external memory or external host processor internal controller manages lap-b protocol including control of the dmac block, transmitter block, and receiver block dmac controls the transfer of data on the external memory to the internal controller or transmitter block, (direct memory and controls the writing of data in the internal controller or receiver block to the external memory access controller) txfifo a 16-byte buffer for when transmit data is sent from the dmac to the transmitter block rxfifo a 32-byte buffer for when receive data is sent from the receiver block to the dmac transmitter converts the contents of txfifo into an hdlc frame and transmits it as serial data receiver receives hdlc frame and writes internal data to rxfifo internal bus an 8-bit address bus and 8-bit data bus that connect the internal controller, dmac, fifo, serial block, and bus interface block d0-d7 a16d8 -a23d15 a0-a15 iord iowr mrd mwr ube cs astb aen ready hldrq hldak crq int clrint b/w pu v cc gnd reset clk bus interface internal controller txfifo transmitter internal bus receiver rxfifo dmac txc txd rts cts cd rxc rxd
3 m pd72107 pin configuration (top view) 64-pin plastic shrink dip (750 mils) m pd72107cw ic rxc rxd txc txd cts ic reset nc ic b/w pu clk gnd a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16d8 a17d9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 rts cd crq aen astb ready hldak hldrq clrint int ube mwr mrd gnd iowr iord v cc d7 d6 d5 d4 d3 d2 d1 d0 a23d15 a22d14 a21d13 a20d12 a19d11 a18d10 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 cs
4 m pd72107 80-pin plastic qfp (14 14 mm) m pd72107gc-3b9 nc hldrq hldak ready astb aen nc crq cd rts nc ic rxc rxd nc txc txd cts ic nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 d1 d0 a23d15 a22d14 a21d13 nc a20d12 a19d11 a18d10 nc nc a17d9 a16d8 a15 a14 a13 a12 a11 a10 nc 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 nc reset ic b/w pu clk gnd gnd nc a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 nc clrint int ube mwr mrd gnd iowr iord cs v cc nc v cc d7 d6 d5 d4 d3 d2 nc
5 m pd72107 68-pin plastic qfj (950 950 mils) m pd72107l reset ic b/w pu clk gnd gnd a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 clrint int ube mwr mrd gnd iowr iord cs v cc v cc d7 d6 d5 d4 d3 d2 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9876543216867666564636261 a10 a11 a12 a13 a14 a15 a16d8 a17d9 nc a18d10 a19d11 a20d12 a21d13 a22d14 a23d15 d0 d1 ic cts txd txc nc rxd rxc ic nc rts cd crq aen astb ready hldak hldr q
6 m pd72107 1. pins 1.1 pin functions sdip qfp qfj active pin no. pin no. pin no. level v cc 47 68 50 C C +5 v power supply 70 51 gnd 14 27 15 C C ground (0 v) 51 28 16 note that there is more than one ground pin. 74 55 clk 13 26 14 i C system clock input (clock) input clock of 1 mhz to 8.2 mhz. reset 8 22 10 i l initializes the internal m pd72107. active width of (reset) more than 7 clk clock cycles is required (clock input is required). after reset, this pin becomes a bus slave. pu 12 25 13 i C pull up to high level when using in normal operation. (pull up) cs 48 71 52 i l when bus master (chip select) set to disable. when bus slave read/write operation from the host processor at low level is enabled. mrd 52 75 56 o l when bus master (memory read) 3-state reads the data of the external memory at low level. when bus slave high impedance mwr 53 76 57 o l when bus master (memory write) 3-state writes the data to the external memory at low level. when bus slave high impedance iord 49 72 53 i l this pin is used when the external host processor (i/o read) reads the contents of the internal registers of the m pd72107. iowr 50 73 54 i l this pin is used when the external host processor (i/o write) writes the data to the internal registers of the m pd72107. astb 60 5 64 o h this pin is used to latch the address output from (address strobe) the m pd72107 externally. i/o pin name function
7 m pd72107 sdip qfp qfj active pin no. pin no. pin no. level nc 9 1, 7, 1 C C use this pin open. (no connection) 11, 15, 5 20, 21, 35 29, 40, 41, 50, 51, 55, 61, 69, 80 ic 1 12 2 C C do not connect anything to this pin. (internally 7 19 9 connected) 10 23 11 ube 54 77 58 i/o l/h when bus master (output) (upper byte 3-state the signal output from this pin changes according enable) to the input value of the b/w pin. ? byte transfer mode (b/w = 0) ube is always high impedance. ? word transfer mode (b/w = 1) indicates that valid data is either in pins d0 to d7 or pins a16d8 to a23d15 (or both). ube a0 d0 to d7 a16d8 to a23d15 00 01 10 11 when bus slave (input) ube pin becomes input, and indicates that valid data is either in pins d0 to d7 or pins a16d8 to a23d15. ube a0 d0 to d7 a16d8 to a23d15 00 01 10 11 i/o pin name function
8 m pd72107 sdip qfp qfj active pin no. pin no. pin no. level b/w 11 24 12 i l/h specifies the data bus that accesses the external (byte/word) memory when bus master. b/w = 0 byte units (8 bits) b/w = 1 word units (16 bits) after power-on, fix the status of the b/w pin. in the case of word access, the lower data bus is the contents data of even addresses. ready 59 4 63 i h an input signal that is used to extend the mrd and (ready) mwr signal widths output by the m pd72107 to adapt to low-speed memory. when the ready signal is low level, the mrd and mwr signals maintain active low. do not change the ready signal at any time other than the specified setup/ hold time. hldrq 57 2 61 o h a hold request signal to the external host processor. (hold request) when a dma operation is performed in the m pd72107, this signal is activated to switch from bus slave to bus master. hldak 58 3 62 i h a hold acknowledge signal from the external host (hold acknowledge) processor. when the m pd72107 detects that this signal is active, the bus slave switches to bus master, and a dma operation is started. aen 61 6 65 o h when bus master, this signal enables the latched (address enable) higher addresses and outputs them to system ad- dress bus. this signal is also used for disabling other system bus drivers. a0, a1 15, 16 30, 31 17, 18 i/o C bidirectional 3-state address lines. 3-state when bus master (output) indicate the lower 2-bit addresses of memory access. when bus slave (input) input addresses when the external host processor i/o accesses the m pd72107. a2 to a15 17 to 30 32 to 47 19 to 32 o C when bus master (except 3-state output bit 2 to bit 15 of memory access addresses. 40, 41) when bus slave become high impedance. i/o pin name function
9 m pd72107 sdip qfp qfj active pin no. pin no. pin no. level a16d8 to a23d15 31 to 38 48 to 58 33 to 41 i/o C bidirectional 3-state address/data buses. multiplex (except 50, (except 35) 3-state pins of the higher 16 bits to 23 bits of addresses 51, 55) and the higher 8 bits to 15 bits of data. d0 to d7 39 to 46 59 to 67 42 to 49 i/o C bidirectional 3-state data buses. (except 61) 3-state when bus master when writing to external memory, these pins become input if reading at output. when bus slave usually, these pins become high impedance. when the external host processor reads i/o of the m pd72107, the internal register data is output. crq 62 8 66 i h a signal requesting command execution to the (command m pd72107 by the external host processor. the request) m pd72107 starts fetching commands from on the external memory at the rising edge of this signal. int 55 78 59 o h an interrupt signal from the m pd72107 to the (interrupt) external host processor. clrint 56 79 60 i h a signal inactivating the int signal being output by (clear interrupt) the m pd72107. the m pd72107 generates the clrint signal in the lsi internal circuit at the rising edge of this signal, and forcibly makes the int output signal low. cts 6 18 8 i C a general-purpose input pin. (clear to send) the m pd72107 reports the cts pin change detection status to the external host processor when the input level of this pin is changed in the general- purpose input/output pin support (setting rssl to 1 by the system initialization command). the change of input level is recognized only when the same level is sampled twice in succession after sampling in 8-ms cycles and detecting the change. moreover, when the external host processor issues a general-purpose input/output pin read command to the m pd72107, the m pd72107 reports the pin information of this pin to the external host processor by a general-purpose input/output pin read response status. the change can be detected even in the clock input stop status of txc and rxc. i/o pin name function
10 m pd72107 sdip qfp qfj active pin no. pin no. pin no. level rts 64 10 68 o C a general-purpose output pin. (request to send) the output value of this pin can be changed by issuing an rts pin write command from the external host processor to the m pd72107. moreover, when the external host processor issues a general-purpose input/output pin read command to the m pd72107, the m pd72107 reports the pin information of this pin to the external host processor by a general-purpose input/output pin read response status. cd 63 9 67 i C a general-purpose input pin. (carrier detect) the m pd72107 reports the cd pin change detection status to the external host processor when the input level of this pin is changed in the general- purpose input/output pin support (setting rssl to 1 by the system initialization command). the change of input level is recognized only when the same level is sampled twice in succession after sampling in 8-ms cycles and detecting the change. moreover, when the external host processor issues a general-purpose input/output pin read command to the m pd72107, the m pd72107 reports the pin information of this pin to the external host processor by a general-purpose input/output pin read response status. the change can be detected even in the clock input stop status of txc and rxc. txd 5 17 7 o C a serial transmit data output pin. (transmit data) txc 4 16 6 i/o C when clk is set to 01 or 10 by operation mode (transmit clock) 3-state setting lcw (output) outputs a clock that divides by 16 the input signal of the rxc pin or clk pin made by the m pd72107. caution txc becomes input because clk = 00 is the default after reset. it becomes output after setting clk to 01 or 10 by operation mode setting lcw. when clk is set to 00 by operation mode setting lcw (input) inputs transmit clock externally. remark lcw: abbreviation for link command word i/o pin name function
11 m pd72107 sdip qfp qfj active pin no. pin no. pin no. level rxd 3 14 4 i C a serial receive data input pin. (receive data) rxc 2 13 3 i C when clk is set to 01 or 10 by operation mode (receive clock) setting lcw sixteen times the clock input of the transmit/receive clock for the on-chip dpll of the m pd72107 when clk is set to 00 by operation mode setting lcw one time the clock input of the receive clock remark lcw: abbreviation for link command word 1.2 pin status after reset of m pd72107 the status of the output pins and input/output pins after reset in the m pd72107 is as shown in table 1-1. table 1-1. pin status after reset pin number 64-pin sdip 80-pin qfp 68-pin qfj 4 16 6 txc i/o note high impedance 5 17 7 txd o h 15, 16 30, 31 17, 18 a0, a1 i/o note high impedance 17 to 30 32 to 47 19 to 32 a2 to a15 o note high impedance (except 40, 41) 31 to 38 48 to 58 33 to 41 a16d8 to a23d15 i/o note high impedance (except 50, 51, 55) (except 35) 39 to 46 59 to 67 42 to 49 d0 to d7 i/o note high impedance (except 61) 52 75 56 mrd o note high impedance 53 76 57 mwr o note high impedance 54 77 58 ube i/o note high impedance 55 78 59 int o l 57 2 61 hldrq o l 60 5 64 astb o l 61 6 65 aen o l 64 10 68 rts o h note 3-state remarks 1. the status after reset is released is the same as the status during reset. 2. input low level to the reset pin for more than 7 clocks of the system clock. i/o pin name function pin name during reset i/o
12 m pd72107 2. electrical specifications absolute maximum ratings (t a = +25 c) parameter symbol conditions ratings unit power supply voltage v dd C0.5 to +7.0 v input voltage v i C0.5 to v dd + 0.3 v output voltage v o C0.5 to v dd + 0.3 v operating ambient temperature t a C40 to +85 c storage temperature t stg C40 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. dc characteristics (t a = C40 to +85 c, v dd = 5 v 10%) parameter symbol conditions min. typ. max. unit input voltage, low v ilc clk pin C0.5 +0.8 v v il other pins C0.5 +0.8 v input voltage, high v ihc clk and pu pins +3.3 v dd + 0.3 v v ih other pins +2.2 v dd + 0.3 v output voltage, low v ol i ol = 2.5 ma 0.4 v output voltage, high v oh i oh = C400 m a 0.7 v dd v power supply current i dd at operation 20 50 ma input leakage current i li 0 v v in v dd 10 m a output leakage current i lo 0 v v out v dd 10 m a capacitance (t a = +25 c, v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f c = 1 mhz C 8 15 pf output capacitance c o unmeasured pins returned to 0 v C 8 15 pf i/o capacitance c io C820pf
13 m pd72107 ac characteristics (t a = C40 to +85 c, v dd = 5 v 10%) when bus master (1) parameter symbol conditions min. max. unit clk cycle time t cyk 121 1000 ns clk low-level time t kkl 50 ns clk high-level time t kkh 50 ns clk rise time t kr 1.5 C 3.0 v 10 ns clk fall time t kf 3.0 C 1.5 v 10 ns load condition caution if the load capacitance exceeds 50 pf due to the configuration of the circuit, keep the load capacitance of this device to within 50 pf by inserting a buffer or by some other means. remark dut: device under test ac test input/output waveform (except clock) system clock dut c l = 50 pf c l includes jig capacitance. 2.2 v 0.8 v 2.2 v 0.8 v 2.4 v 0.4 v test points t kf t kr t kkl t kkh t cyk 1.5 v 3.0 v clk
14 m pd72107 when bus master (2) parameter symbol conditions min. max. unit hldrq - delay time (vs. clk )t dhqh 100 ns hldrq delay time (vs. clk - )t dhql 100 ns hldak setup time (vs. clk - )t sha 35 ns hldak hold time (vs. clk - )t hha 20 ns aen - delay time (vs. clk )t daeh 100 ns aen delay time (vs. clk - )t dael 100 ns astb - delay time (vs. clk - )t dsth 70 ns astb high-level width t ststh t kkh C15 ns astb delay time (vs. clk )t dstl 100 ns adr/ube/mrd/mwr delay time t da 100 ns (vs. clk - ) adr/ube/mrd/mwr float time t fa 70 ns (vs. clk - ) adr setup time (vs. astb )t sast t kkh C35 ns adr hold time (vs. astb )t hsta t kkl C20 ns mrd delay time (vs. adr float) t dar 0ns mrd delay time (vs. clk - )t drl 70 ns mrd low-level width t rrl2 2t cyk C50 ns mrd - delay time (vs. clk - )t drh 70 ns data setup time (vs. mrd - )t sdr 100 ns data hold time (vs. mrd - )t hrd 0ns mwr delay time (vs. clk - )t dwl 70 ns mwr low-level width t wwl2 2t cyk C50 ns mwr - delay time (vs. clk - )t dwh 70 ns ready setup time (vs. clk - )t sry 35 ns ready hold time (vs. clk - )t hry 20 ns
15 m pd72107 when bus master t dhqh t sha t hha t daeh t dsth t dstl t da t ststh t sast t hsta t dwl t fa t sry t sry t da t dar t drl t rrl2 t drh t sdr t hrd t fa t hry t dwh t hry t wwl2 t dael t dhql hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z address input data output data address clk hldrq hldak aen astb a16d8-a23d15 a0, a1/a2-a15 ube mwr ready a16d8-a23d15 mrd address t hha
16 m pd72107 when bus slave (1) parameter symbol conditions min. max. unit iowr low-level width t wwl 100 ns cs low-level hold time t hwcs 0ns (vs. iowr - ) adr/ube/cs low-level setup time t saw 0ns (vs. iowr ) adr/ube hold time (vs. iowr - )t hwa 0ns data setup time (vs. iowr - )t sdw 100 ns data hold time (vs. iowr - )t hwd 0ns iord low-level width t rrl 150 ns adr/cs low-level setup time t sar 35 ns (vs. iord ) adr/cs low-level hold time t hra 0ns (vs. iord - ) data delay time (vs. iord )t drd 120 ns data float time (vs. iord - )t frd 10 100 ns reset low-level width t rstl 7t cyk ns v dd setup time (vs. reset - )t svdd 1000 ns reset - C1st ? iowr/iord t sywr 2t cyk ns iowr/iord recovery time t rvwr 200 ns
17 m pd72107 when bus slave t saw t wwl t hwcs t hwa t hwd t sdw t sar t rrl t hra t drd t frd t svdd t rstl t sywr t rvwr t rvwr t rvwr t rvwr cs iowr a0-a23 ube d0-d15 cs a0-a23 iord d0-d15 v dd reset iord iowr iord/iowr hi-z hi-z
18 m pd72107 when bus slave (2) parameter symbol conditions min. max. unit iowr/iord high-level setup time t swr C20 ns (vs. hldak - ) iowr/iord high-level hold time t hwr 100 ns (vs. aen ) when bus slave (3) parameter symbol conditions min. max. unit clrint high-level width t clclh 100 ns int - delay time (vs. clk - )t dih 100 ns int delay time (vs. clrint - )t dil 100 ns crq high-level width t crcrh 100 ns t swr t hwr hldak iowr/iord aen iowr/iord t clclh t dil t crcrh t dih clk clrint int crq
19 m pd72107 serial block (1) parameter symbol conditions min. max. unit txc/rxc cycle time t cys when on-chip dpll is not used 250 dc ns txc/rxc low-level time t ssl 110 ns txc/rxc high-level time t ssh 110 ns txc/rxc rise time t sr 20 ns txc/rxc fall time t sf 12 ns txd delay time (vs. txc )t dtxd 100 ns rxd setup time (vs. rxc - )t srxd 50 ns rxd hold time (vs. rxc - )t hrxd 70 ns serial clock (when on-chip dpll is not used) t sf t sr t ssl 0.8 v 2.2 v t ssh t cys t dtxd t dtxd t srxd t hrxd txc/rxc txc (input) txd rxc rxd
20 m pd72107 serial block (2) parameter symbol conditions min. max. unit rxc cycle time t cyr when on-chip dpll is used (source clock = rxc) 30.3 ns when on-chip dpll is used (source clock = clk) 125 1000 rxc low-level time t ssrl when on-chip dpll is used (source clock = rxc) 10 ns when on-chip dpll is used (source clock = clk) 50 rxc high-level time t ssrh when on-chip dpll is used (source clock = rxc) 10 ns when on-chip dpll is used (source clock = clk) 50 rxc rise time t srr when on-chip dpll is used (source clock = rxc) 5 ns when on-chip dpll is used (source clock = clk) 10 rxc fall time t srf when on-chip dpll is used (source clock = rxc) 5 ns when on-chip dpll is used (source clock = clk) 10 transmit/receive data cycle t cyd when on-chip dpll is used (source clock = rxc) 500 ns when on-chip dpll is used (source clock = clk) 2000 16000 txc low-level time t tctcl when on-chip dpll is used 0.5t cyd C25 ns txc high-level time t tctch 0.5t cyd C25 ns txd delay time (vs. txc )t dtctd 50 ns txd hold time (vs. txc - )t htctd 0.5t cyd C25 ns serial clock (when on-chip dpll is used) t cyr t ssrl t srf t tctcl t dtctd t tctch t htctd t cyd t srr t ssrh txc txd rxc
21 m pd72107 serial block (3) parameter symbol conditions min. max. unit rts - delay time (vs. clk - )t drth 100 ns rts delay time (vs. clk - )t drtl 100 ns cd setup time (vs. clk - )t scd 35 ns cd hold time (vs. clk - )t hcd 20 ns cts setup time (vs. clk - )t sct 35 ns cts hold time (vs. clk - )t hct 20 ns t drtl t hcd t drth t scd t sct t hct rts clk cd cts
22 m pd72107 3. application circuit example (1) connection with sifc ( m pd98201) rxd txd bina bout1 sifc lap-b bclk txc rxc pd72107 pd98201 mm
23 m pd72107 4. system configuration examples rd wr cs ube a0-a15 d0-d15 local memory 64 kbytes a0-a15 d0-d15 oe pd71086 a b oe pd71086 a b oe pd71086 a b oe pd71086 a b access contention resolution circuit memr memw ior iow ab0-ab7 ab8-ab15 ab16-ab19 bhe db0-db15 int local bus request wait mrd mwr iord iowr cs a0-a15 d0-d7 a16d8-a23d15 ube aen int hldrq hldak host processor pd72107 m m m m m pd72107 system configuration example (local memory type) m decoder
24 m pd72107 int iord iowr cs mrd mwr hldrq hldak aen astb d0-d7 a16d8-a23d15 a0-a15 ube oe stb pd71082 decoder a0-a15 a16-a19 d8-d15 d0-d7 intp cs a0 pd71059 int intak rd wr d0-d7 pd71082 3 stb oe pd71086 2 toe rd wr cs ube d0-d7 d8-d15 memory pd70116 int intak rd wr hldrq hldak astb a16-a19 ad8-ad15 ad0-ad7 ube buf r/w bufen host processor pd72107 m m m m m pd72107 system configuration example (main memory sharing type) m m
25 m pd72107 i j g h f d n m cb m r 64 33 32 1 k l notes 1. controlling dimension millimeter. p64c-70-750a,c-3 item millimeters inches b c d f g h j k 1.778 (t.p.) 3.2?.3 0.51 min. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0?.2 n 0 to 15 0.500.10 0.9 min. r 0.070 max. 0.020 0.035 min. 0.1260.012 0.020 min. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0 to 15 +0.004 e0.003 0.070 (t.p.) +0.10 e0.05 +0.004 e0.005 64 pin plastic shrink dip (750 mil) 2. each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. 3. item "k" to center of leads when formed parallel. a 58.0 2.283 +0.028 ?.008 +0.68 ?.20 i 4.05 0.159 +0.011 ?.008 +0.26 ?.20 a +0.009 ?.008 5. package drawings
26 m pd72107 80 pin plastic qfp (14x14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. l 0.8?.2 0.031 +0.009 ?.008 m 0.15 0.006 n 0.10 0.004 a 17.2?.4 0.677?.016 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 17.2?.4 0.677?.016 f 0.825 0.032 g 0.825 0.032 h 0.30?.10 0.012 +0.004 ?.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) q 0.1?.1 0.004?.004 r5 5 5 5 +0.10 e0.05 +0.004 e0.003 m m l k j h q p n r detail of lead end i g k 1.60.2 0.0630.008 60 61 40 80 1 21 20 41 a b cd f s s80gc-65-3b9-5 s 3.0 max. 0.119 max. p 2.7?.1 0.106 +0.005 ?.004
27 m pd72107 68 1 + 0.08 - 0.07 s a b cd h m p j i g u t k e f item millimeters inches b 24.20 0.1 0.953 d 25.2 0.2 0.992 0.008 e 1.94 0.15 0.076 + 0.007 - 0.006 f 0.6 0.024 a 25.2 0.2 0.992 0.008 c 24.20 0.1 0.953 + 0.004 - 0.005 g 4.4 0.2 0.173 h 2.8 0.2 0.110 i 0.9 min. 0.035 min. j 3.4 0.1 0.134 k 1.27 (t.p.) 0.050 (t.p.) m 0.42 0.08 0.017 n 0.12 0.005 q 0.15 0.006 t r 0.8 r 0.031 u 0.22 0.009 + 0.004 - 0.005 + 0.009 - 0.008 + 0.009 - 0.008 + 0.004 - 0.005 + 0.003 - 0.004 + 0.003 - 0.004 s m p68l-50a1-3 q n notes 1. controlling dimension millimeter. 2. each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. 68 pin plastic qfj (950 x 950 mil) p 23.12 0.2 0.910 + 0.009 - 0.008
28 m pd72107 6. recommended soldering conditions the m pd72107 should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. surface mounting type ? m pd72107gc-3b9: 80-pin plastic qfp (14 14 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. ir35-00-3 (at 210 c or higher), count: three times or less vps package peak temperature: 215 c, time: 40 sec. max. vp15-00-3 (at 200 c or higher), count: three times or less wave soldering solder bath temperature: 260 c, time: 10 sec. max., ws60-00-1 count: one time, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., duration: 3 sec. max. (per pin row) C caution do not use different soldering methods together (except for partial heating). ? m pd72107l: 68-pin plastic qfj (950 950 mils) soldering method soldering conditions recommended condition symbol vps package peak temperature: 215 c, time: 40 sec. max. vp15-00-1 (at 200 c or higher), count: one time partial heating pin temperature: 300 c max., duration: 3 sec. max. (per pin row) C insertion type ? m pd72107cw: 64-pin plastic shrink dip (750 mils) soldering method soldering conditions wave soldering (pin only) solder bath temperature: 260 c max., time: 10 sec. max. partial heating pin temperature: 300 c max., duration: 3 sec. max. (per a pin) caution wave soldering must be applied only to pins. be sure to avoid jet soldering the package body.
29 m pd72107 [memo]
30 m pd72107 [memo]
31 m pd72107 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
2 m pd72107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of this product from japan is prohibited without governmental license. to export or re-export this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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